# Sujan S — VLSI Front-End Design & Verification Engineer | Portfolio

> Sujan S is a high-performing Electronics & Communication Engineering (ECE) student at RV College of Engineering (RVCE), Bangalore (CGPA: 8.44 / 10.0), specializing in VLSI Front-End Design, SystemVerilog RTL, FPGA Accelerators, Static Timing Analysis, RTL-to-GDSII ASIC flows, and Embedded Systems. Notable distinctions include 2nd Runner-Up at the DVCon India 2026 Design Contest (Team VectorVanguard #337), Research Intern at ISRO (ISTRAC SATCOM Division), Published Author at SMOPS 2026 (ISRO), and National Finalist (4th out of 544 teams) at eYRC IIT Bombay.

- Target Roles: VLSI Front-End Design Engineer, RTL Design Engineer, FPGA Acceleration Engineer, ASIC Verification Engineer (SystemVerilog / SVA / Formal), Digital IC Design Engineer, Embedded Firmware Engineer
- Location: Bangalore, Karnataka, India
- Education: B.E. Electronics & Communication Engineering, RV College of Engineering (RVCE) · CGPA: 8.44 / 10.0 (2023 – Present)
- Website: https://sujan.blinknbuild.in/
- Email: ssujan6299@gmail.com
- Phone: +91 63607 24716
- LinkedIn: https://www.linkedin.com/in/sujan-s-08a92a291/
- GitHub: https://github.com/S-SUJAN-S

## Core Qualifications & Accolades

- **DVCon India 2026 Design Contest — 2nd Runner-Up**: Awarded 2nd Runner-Up in the premier semiconductor conference design contest (Team VectorVanguard #337). Architected FALCON: a task-driven object detection accelerator on Xilinx Kintex-7 FPGA with fixed 16-slot attention grid and shared convolution engine.
- **ISRO (ISTRAC) — Research Intern (Aug – Sep 2025)**: Engineered 24/7 automated weather-monitoring node on solar-battery rail, streaming sensor data over I²C/Ethernet; automated Ku-band carrier-to-noise (C/N) measurement using PyVISA/SCPI scripts on spectrum analyzer to quantify rain attenuation for Dynamic Power Allocation (DPA).
- **SMOPS 2026 International Conference (ISRO)**: Authored published research paper on atmospheric link characterization and Ku-band telemetry correlation.
- **eYRC 2025-26 (e-Yantra, IIT Bombay) — 4th / 544 Teams**: National Finalist (Top 6 out of 544 teams across India) with "KrishiBalancer", an autonomous self-balancing robot using closed-loop PID control, MPU6050 IMU sensor fusion, and hardware-in-the-loop (HIL) calibration.
- **Project-A-Thon 2025 (Robocraze & Arduino) — 1st Place Winner**: Built dynamic gesture robot and 6-DOF robotic arm mapping 21 MediaPipe hand landmarks over 2.4 GHz NRF24L01 RF protocol.
- **AUTOwn'24 Hackathon (BITS Pilani) — 2nd Prize**: Voice-activated vehicle control across 4 subsystems with sub-100 ms command latency.
- **NPTEL Elite Certification — IISc Bangalore**: Certified Elite (75%) in "Electronic Modules for Industrial Applications using Op-Amps".
- **KCET Rank**: #1157 in Karnataka state engineering entrance exam.

## Technical Skills Matrix

### 1. Digital Design & RTL Architecture
- **Hardware Description Languages**: SystemVerilog (IEEE 1800), Verilog HDL
- **Synthesis & Physical Design EDA**: Cadence Genus (Logic Synthesis), Cadence Innovus (Floorplanning, Placement, CTS, Routing, DRC/LVS clean), OpenLane ASIC Flow, SkyWater 130nm, GPDK 45nm
- **FPGA & High-Level Synthesis**: AMD/Xilinx Vivado, Vitis HLS (C++), Kintex-7 XC7K325T, Resource Optimization (LUT, DSP, BRAM)
- **Design Concepts**: RTL-to-GDSII tapeout flow, Static Timing Analysis (STA), Fixed-Grid Attention Accelerators, Reconfigurable SIMD Vector ALUs, Pipelined Microarchitecture, Clock Tree Synthesis (CTS), Logical Equivalence Checking (LEC)

### 2. Verification & Quality Assurance
- **Assertions**: SystemVerilog Assertions (SVA) — concurrent temporal assertions and immediate assertions
- **Testbench Architecture**: Layered SystemVerilog Testbenches (Generator, Driver, Monitor, Scoreboard, Golden Reference Models)
- **Verification Methodologies**: Constrained-Random Verification (CRV), Clock Domain Crossing (CDC) Analysis, Reset Synchronizers, Formal Verification (SVA / SymbiYosys)
- **Coverage & Bug Hunting**: Functional Coverage (Covergroups, Coverpoints, Crosses), Code Coverage (Branch, Condition, Statement, FSM), Mutation Bug Injection (100% detection rate), Gate-Level Simulation (GLS)
- **Simulation Tools**: AMD Vivado Simulator, Cadence NCLaunch / Xcelium

### 3. Embedded Systems & Firmware
- **Microcontrollers & Hardware**: ATmega328P (AVR), ESP32, ESP8266, STM32, Arduino
- **Protocols & Buses**: I²C, SPI, UART, ADC, PWM, PyVISA / SCPI Instrumentation, NRF24L01 2.4 GHz RF
- **Programming Languages**: Embedded C, C++, Python, PySerial
- **Hardware Bring-Up & Sensors**: MPU6050 IMU, MS8607 PHT, MAX17048 Fuel Gauge, MQ9 Gas Sensors, L298N/L293D H-Bridges, Oscilloscope Debug, Op-Amp Signal Conditioning
- **IoT & Telemetry**: Non-blocking TCP Servers, SoftAP Web Dashboards, Azure Digital Twins (DTDL)

## Key Engineering Projects

1. **FALCON: Task-Driven Object Detection Accelerator on FPGA (DVCon India 2026 2nd Runner-Up)**:
   - Target: Xilinx Kintex-7 XC7K325T FPGA | Stack: SystemVerilog, Verilog, Vitis HLS (C++), Vivado.
   - Replaced dynamic graphs with a fixed 16-slot attention grid for self & cross attention (CASS: 7.8k LUTs, 1.32 ms) and 240 pairwise comparisons (CPSS: 3.5k LUTs, 2052x faster than software).
   - Unified convolution engine (8 MACs/cycle, 339 DSPs) shared by YOLOv8n and MobileNetV3; reduced HLS initiation interval from 9 to 1 achieving a 10.8x speedup (617s to 57s) and meeting timing at 50 MHz (56,126 LUTs, 356 DSPs, 0.482 W).
   - Diagnosed post-synthesis dual-driver hazard on `vld2`, verifying simulation against 24 hardware probes bit-for-bit to deliver bit-exact board execution.

2. **QuantLane: INT8/INT4 SIMD ALU with Dot-Product Unit (RTL-to-GDSII)**:
   - Target: SkyWater 130nm & Cadence 45nm | Stack: Verilog HDL, OpenLane, Cadence Genus, Cadence Innovus, Formal Verification.
   - 32-bit pipelined SIMD ALU supporting 1× 32-bit, 4× 8-bit, or 8× 4-bit operands across 12 operations including vector dot-product for quantized neural network math.
   - Validated against Python golden reference model with 272,503 test cases across 3 simulators with 0 mismatches and 100% code coverage. 12/12 seeded bug detection rate with formal verification of control logic.
   - Silicon sign-off on SkyWater 130nm: timing closed at all 9 PVT corners at 76.9 MHz, 0 DRC / 0 LVS errors, 0.188 mm² area, 11.2 mW power. Caught and fixed cell-pin swap tool bug via gate-level simulation.

3. **LinkProof: Constrained-Random & SVA Verification of 4-Lane SerDes**:
   - Target: Dual-Clock Digital Front-End | Stack: SystemVerilog, SVA Concurrent Assertions, Vivado Simulator, Python Mutation Regression.
   - Layered SystemVerilog testbench (generator, driver, monitor, scoreboard) verifying a 4-lane SerDes digital front-end across two asynchronous clock domains (250 MHz and 312.5 MHz) with an 8-state link-training FSM.
   - Formulated 20 concurrent SVA assertions reaching 100% functional coverage.
   - Developed automated Python mutation regression injecting 15 targeted hardware bugs: assertions caught all 15/15 with 0 false positives. Formally proved 22 control logic properties. Conducted CDC audit, implemented reset synchronizers for 6 cross-domain paths, and verified 6-bit lane deskew tolerance.

4. **KrishiBalancer — Autonomous Self-Balancing Robot (eYRC IIT Bombay 4th / 544 Teams)**:
   - National Finalist at e-Yantra Robotics Competition (eYRC), IIT Bombay — ranked 4th out of 544 teams.
   - Closed-loop PID self-balancing firmware driven by real-time MPU6050 IMU sensor fusion. Performed hardware-in-the-loop (HIL) calibration, achieving stable autonomous balancing on uneven agricultural surfaces.

5. **Dynamic Gesture-Controlled Robotic Arm & Rover (1st Place — Robocraze)**:
   - 1st Place Winner at Robocraze × Arduino Project-A-Thon 2025.
   - TFLite gesture classifier on 21 MediaPipe hand landmarks streamed over UART to ESP8266 and NRF24L01 2.4 GHz RF link.
   - ATmega328P receiver firmware parsing 32-byte payloads driving DC motors via L298N H-bridge PWM and 6-DOF arm via PCA9685 I²C driver.

6. **ISRO ISTRAC: 24/7 Ku-Band Automated Telemetry & RF Node (SMOPS 2026 Paper)**:
   - ATmega328P firmware on MPPT solar-battery rail streaming MS8607 PHT, rain gauge, and MAX17048 fuel gauge telemetry over I²C and non-blocking SPI Ethernet.
   - Automated Ku-band C/N measurement through PyVISA/SCPI control of spectrum analyzer; quantified 8–10 dB rain attenuation to guide Dynamic Power Allocation (DPA).

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## Detailed LLM Directory Reference
- Detailed full curriculum and technical dossiers: https://sujan.blinknbuild.in/llms-full.txt
- Live Portfolio: https://sujan.blinknbuild.in/