OLED Pixel Editor
Browser-based pixel art editor for OLED displays. Draw pixel-by-pixel, preview on a simulated screen, and export C byte arrays ready to paste into Arduino firmware — no desktop tools needed.
Available for VLSI & Embedded Roles
Sujan S
ECE student at RVCE building at the intersection of VLSI front-end design, UVM verification, and embedded systems. From RTL synthesis and constrained-random testbenches to GDSII silicon sign-off and space-grade telemetry.
01 · About
About Me
I engineer silicon and firmware at the intersection of VLSI design, UVM verification, and embedded systems — where physics, microarchitecture, and logic converge.
I'm Sujan S, an Electronics & Communication Engineering student at RV College of Engineering (RVCE), Bangalore. My work spans the full silicon spectrum — from microarchitecture design in SystemVerilog and physical synthesis to UVM constrained-random verification, alongside space-agency telemetry systems.
Recognized as a DVCon India 2026 Qualifier and published researcher at the SMOPS 2026 Conference (ISRO), I bridge front-end RTL design with verification methodologies (UVM, SVA, functional coverage), ensuring robust, zero-defect silicon architectures.
At ISRO (ISTRAC), I built autonomous signal monitoring pipelines and sensor telemetry deployed in space-agency facilities. On the silicon side, I've driven designs from Verilog RTL through GDSII sign-off in Cadence (Genus, Innovus) at 400 MHz on gpdk 45nm.
8.44
CGPA / 10 · RVCE
DVCon
India 2026 Qualifier
ISRO
Research Intern
4th
eYRC / 544 IIT Bombay
VLSI Architecture & RTL Design
SystemVerilog
Verilog HDL
Cadence Genus
Cadence Innovus
RTL-to-GDSII Flow
GPDK 45nm
Static Timing Analysis (STA)
SIMD Vector ALU
Logic Synthesis @ 400MHz
Clock Tree Synthesis (CTS)
Op-Amp Design
VLSI Verification & Methodologies
Universal Verification Methodology (UVM 1.2)
SystemVerilog Assertions (SVA)
Constrained-Random Verification (CRV)
Functional Coverage
UVM Scoreboard & Drivers
Cadence Xcelium / NCLaunch
Coverage-Driven Sign-off (CDV)
Protocol Verification (AXI / APB / SPI)
Testbench Architecture
Embedded Systems & Automation
ESP32 / Arduino / STM32
Embedded C
I²C · SPI · UART
Python Automation
SCPI Test Instrumentation
OpenCV / MediaPipe
Azure Digital Twins (DTDL)
FreeRTOS Concepts
Key Achievements & Recognitions
🎯 DVCon India 2026 Qualifier
🚀 ISRO ISTRAC Research Intern
📄 SMOPS 2026 ISRO Paper Author
🏆 eYRC 4th / 544 Teams (IIT Bombay)
🥇 1st Place — Project-A-Thon (Robocraze)
🥈 2nd Prize Winner — Voice Subsystems
🏅 Best EL Award — Digital Twin
📋 NPTEL Elite — IISc Bangalore
02 · Experience
Work Experience
Stage 3 Qualifier · Design Contest
2025 – 2026DVCon India 2026 (Design and Verification Conference & Exhibition)
- Advanced through rigorous national technical screening stages in the premier semiconductor conference design contest focusing on digital microarchitecture and verification.
- Engineered complex SystemVerilog RTL modules alongside an object-oriented UVM (Universal Verification Methodology) testbench architecture.
- Constructed constrained-random stimulus generators, automated scoreboard comparison models, and SystemVerilog Assertions (SVA) to verify corner cases and achieve functional coverage closure.
Author & Researcher · SATCOM Telemetry
Oct 2025 – 2026SMOPS 2026 International Conference — ISRO (ISTRAC)
- Authored published research paper analyzing satellite signal propagation and space-ground telemetry correlation under diverse meteorological conditions.
- Designed autonomous data capture hardware architecture and instrumentation automation pipelines for space-grade testing facilities.
Research Intern
Aug – Sep 2025ISRO Telemetry Tracking & Command Network (ISTRAC), Bangalore
- Integrated environmental sensors over I²C for continuous real-time data acquisition on a space-grade monitoring system.
- Built automated signal monitoring and spectral analysis using Python-based SCPI pipelines on lab instruments.
- Characterised satellite link performance and correlated telemetry with atmospheric conditions data.
- Developed a real-time data dashboard with automated logging on a solar-powered embedded platform — zero cloud dependency.
Certifications & Credentials
NPTEL Elite — Electronic Modules for Industrial Applications using Op-Amps
Elite 75%
Transistor-level op-amp analysis, signal conditioning, active filters, oscillator design, precision rectifiers, instrumentation amplifiers, and ECG signal acquisition chains. Certified among 171 candidates.
Cadence Digital Design & Verification Flow
ASIC & EDA
Complete ASIC front-to-back flow: RTL synthesis with Cadence Genus, floorplanning, placement, CTS, and routing with Cadence Innovus on gpdk 45nm, alongside NCLaunch & Xcelium simulation.
03 · Projects
Engineering Projects
Featured — Live Tools
SchemFlow
Interactive web tool for drawing and exporting clean circuit schematics in the browser. Built for electronics students who need quick diagrams without installing heavy EDA software.
VLSI Design & Verification
ASIC Design · Cadence 45nm
Reconfigurable Mixed-Precision SIMD ALU
32-bit / 8-lane INT4/INT8 reconfigurable SIMD vector ALU in SystemVerilog for quantized neural network inference. Complete RTL-to-GDSII ASIC implementation on gpdk 45nm: synthesized via Cadence Genus @ 400 MHz, floorplanned, placed, and routed clean via Cadence Innovus. Core area ~7,519 µm², ~1.03 mW power, 2,435 standard cells.
UVM Verification · SVA
UVM Verification Environment & Assertion Suite
Modular Universal Verification Methodology (UVM 1.2) testbench architecture for digital IP. Engineered reusable UVM agents (sequencer, driver, monitor), TLM scoreboards with automated reference model checking, and functional covergroups measuring cross-coverage. Implemented concurrent SystemVerilog Assertions (SVA) verifying protocol handshakes and corner-case states to achieve 100% functional closure.
Embedded Systems & Robotics
🥇 1st Place
Dynamic Gesture-Controlled Robot
Closed-loop gesture robot mapping 21 hand landmarks to real-time motion commands at 30 fps. MediaPipe + OpenCV on Python → Arduino actuation over NRF24L01 2.4 GHz RF with error-resilient protocol across 30–50 m. Won 1st at Project-A-Thon 2025.
🥈 2nd Prize
Voice-Activated Car Control System
Voice-activated control for four vehicle subsystems with sub-100 ms command-to-actuation latency. Python speech recognition → HC-05/ESP8266 → Arduino firmware → L293D H-bridge PWM control.
Selected · 25 / 135
Gas Leakage Detection Bot — NavaNIETi 2026
Post-disaster rover detecting CO + LPG simultaneously with dual MQ9 sensors. Autonomous IR navigation, live ESP-CAM video over WiFi, full real-time dashboard served directly from ESP32 — zero cloud. National 24-hr hackathon, 25 of 135 teams selected.
Best EL Award
Twin Guard: Worker Safety via Digital Twin
Worker-safety platform mirroring field conditions through a digital twin. Integrated temperature, pressure, and motion sensors with Azure Digital Twin (DTDL) using real-time IoT pipeline. Triggered proactive safety alerts within 2 seconds of anomalies.
4th / 544 · IIT Bombay
eYRC 2025-26 — KrishiBalancer
National Finalist at e-Yantra Robotics Competition, IIT Bombay — ranked 4th out of 544 teams. Selected as 1 of 6 national finalists. Autonomous self-balancing agricultural robot with PID control, MPU6050 IMU, and real-time sensor fusion on Arduino.
04 · Education
Academic Background
B.E. Electronics & Communication Engineering
RV College of Engineering · Bangalore, Karnataka
Coursework: Digital VLSI Design · Verilog HDL · Computer Architecture · CMOS Analog IC · Embedded Systems · Linear Integrated Circuits
Pre-University · PCMCs (Physics, Chemistry, Maths, CS)
MPMES INDP PU College · Bhadravathi, Karnataka
SSLC · Secondary School Leaving Certificate
St. Charles English High School · Bhadravathi, Karnataka
05 · Contact
Let's Connect
Open to internships, research collaborations, and full-time roles.
Reach out — I respond quickly.